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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI49FCT3807D
1-10 Clock Buffer for Networking Applications
Description
Product Features
High Frequency >156 MHz High-speed, low-noise, non-inverting 1-10 buffer Low-skew (<250ps) between any two output clocks Low duty cycle distortion <250ps Low propagation delay <2.5ns Multiple VDD, GND pins for noise reduction 3.3V supply voltage Available in SOIC, SSOP, and QSOP packages
The PI49FCT3807D is a 3.3V compatible, high-speed, low-noise 1-10 non-inverting clock buffer. The key goal in designing the PI6C3807D is to target networking applications that require lowskew, low-jitter, and high-frequency clock distribution. Providing output-to-output skew as low as 150ps, the PI49FCT3807D is an ideal clock distribution device for synchronous systems. Designing synchronous networking systems requires a tight level of skew from a large number of outputs.
Block Diagram
Pin Configuration
CLK0
BUF_IN GND
1 2 3 4 5 6 7 8 9 10
20 19 18
VDD CLK9 CLK8 GND CLK7 VDD CLK6 GND CLK5 CLK4
CLK1 BUF_IN CLK2
CLK0 VDD CLK1 GND
20-Pin H,Q,S
17 16 15 14 13 12 11
CLK3
CLK2 VDD CLK3
CLK9
GND
1
PS8493
08/09/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI49FCT3807D 1-10 Clock Buffer for Networking Applications
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ........................................................... 65C to +150C VDD Voltage ........................................................................... 0.5V to +4.6V Output Voltage ................................................................ 0.5V to VDD+0.5V Input Voltage ......................................................................... 0.5V to +7.0V DC Output Current ............................................................. 60mA to +60mA Power Dissipation ............................................................................. 500mW Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Range
VDD Voltage ................................................................................. 3.3V 0.3V Commercial Temperature ......................................................... 0C to +70C Industrial Temperature ............................................................. 40V to +85V Input Frequency .................................................................... DC to 156 MHz Capacitive Loading ................................................................... 10pF to 50pF
DC Electrical Characteristics (Over the Operating Range)
Parame te rs VIH VIL IIH IIL VIK VOH VOL IOH IOL De s cription Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Clamp Diode Voltage Output HIGH Voltage Te s t Conditions (1) Guaranteed Logic HIGH Level (Input Pins) Guaranteed Logic LOW Level (Input Pins) VDD = Max. VDD = Max. VDD = Min., IIN = 18mA VDD = Min., VIN = VIH or VIL VDD = Min., VIN = VIH or VIL IOH = 0.1mA IOH = 12mA IOL = 0.1mA IOL = 12mA 1.5V(4) VIN = VDD VIN = GND M in. 2.0 0.5 VDD 0.2 2.4(3) 45 50 Typ.(2) 0.7 3.0 0.3 75 92 M ax. 5.5 0.8 1 1 1.2 0.2 0.5 180 200 mA V Units V A
Output LOW Voltage
Output HIGH Current VDD = 3.0V, VIN = VIH or VIL, VOUT = Output LOW Current
VDD = 3.0V, VIN = VIH or VIL, VOUT = 1.5V(4)
Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient and maximum loading. 3. VOH = VCC 0.6V at rated current. 4. This parameter is determined by device characterization but is not production tested. 5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
2
PS8493
08/09/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI49FCT3807D 1-10 Clock Buffer for Networking Applications
Power Supply Characteristics
Parame te rs IDDQ IDD De s cription Quiescent Power Supply Current Supply Current per Inputs @ TTL HIGH VDD = Max. VDD = Max. Te s t Conditions (1) VIN = GND or VDD VIN = VDD 0.6V(3) 50 MHz 67 MHz IDD Dynamic Supply Current VDD = 3.6V, No Load 80 MHz 100 MHz 125 MHz 156 MHz M in. Typ.(2) 0.1 47 43 56 66 81 97 121 M ax. 30 300 mA A Units
Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at VDD = 3.3V, +25C ambient. 3. Per TTL driven input (VIN = VDD 0.6V); all other inputs at VDD or GND.
Capacitance (TA = 25C, f = 1 MHz)
Parameters(1) CIN C OUT Description Input Capacitance Output Capacitance Test Conditions VIN = 0V VOUT = 0V Typ 3.0 Max. 4 6 Units pF
Note: 1. This parameter is determined by device characterization but is not production tested.
Product Pin Description
Pin Name BUF_IN CLK [0:9] GND VDD Description Input Outputs Ground Power
Test Circuits for All Outputs
VDD
VIN Pulse Generator D.U.T.
VOUT
Definitions: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance, should be equal to Zout of the Pulse Generator.
CL
3
PS8493
08/09/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI49FCT3807D 1-10 Clock Buffer for Networking Applications
Switching Characteristics (VCC = 3.3V 0.3V, TA = 85C)
Parame te rs tR/tF tPLH tPHL tSK(o)(3) tSK(p)(3) tSK(t)(3) De s cription CLKn Rise/Fall Time 0.8V~2.0V Propagation Delay BUF_IN to CLKn Skew between two outputs of the same package (same transition) Skew between opposite transitions (tPHL- tPLH) of the same output Skew between two outputs of different package (4) Te s t Conditions (1) CL = 15pF, 125 MHz CL = 15pF, 125 MHz CL = 15pF, 125 MHz CL = 15pF, 125 MHz CL = 15pF, 125 MHz M in. 1.0 Typ. 0.7 2.2 110 200 M ax. Units 1.0 2.5 250 ps 250 0.55 ns ns
Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew measured at worse cast temperature (max. temp). 4. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.
4
PS8493
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI49FCT3807D 1-10 Clock Buffer for Networking Applications
SWITCHING WAVEFORMS
Propagation Delay Pulse Skew tSK(P)
3V Input 1.5V 0V tPLH tPHL VOH Output 1.5V VOL
3V Input 1.5V 0V tPLH tPHL VOH
2.0V
Output
1.5V
0.8V
VOL tR tF
tSK(p) =
tPHL tPLH
Output Skew tSK(O)
3V Input 1.5V 0V tPLHx tPHLx VOH CLKx 1.5V VOL tSK(o) tSK(o) VOH CLKy 1.5V VOL tPLHy tPHLy
Package Skew tSK(T)
3V Input 1.5V 0V tPLH1 Package 1 Output tSK(t) Package 2 Output tPLH2 tPHL2 tSK(t) VOH 1.5V VOL tPHL1 VOH 1.5V VOL
tSK(o) =
tPLHy
tPLHx
or tPHLy
tPHLx
tSK(t) =
tPLH2
tPLH1
or tPHL2
tPHL1
5
PS8493
08/09/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI49FCT3807D 1-10 Clock Buffer for Networking Applications
20-Pin SOIC (S20) Package
20
20-Pin SSOP (H20) Package
20
.2914 7.40 .2992 7.60 .010 .029 1 .496 12.60 .511 12.99 .0091 .0125 0.41 .016 1.27 .050 .0926 2.35 .1043 2.65 SEATING PLANE .394 .419 10.00 10.65 0.23 0.32 0.254 x 45 0.737
1 .272 .295 6.90 7.50
.197 .220
5.00 5.60
.004 .009
0.09 0.25
0-8
.078 2.00 Max SEATING PLANE .002 Min 0.050
0.55 .022 0.95 .037 .291 .322 7.40 8.20
.020 0.508 REF .030 0.762
.0256 BSC 0.65
.0098 Max. 0.25
.050 BSC 1.27
.013 .020 0.33 0.51
.0040 .0118
0.10 0.30 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
20-Pin QSOP (Q20) Package
20
.150 .157
3.81 3.99 .015 x 45 0.38
1 .337 8.56 .344 8.74 .016 0.41 .050 1.27 .053 1.35 .069 1.75 SEATING PLANE .228 .244 5.79 6.19 .007 0.178 .010 0.254
.058 REF 1.47
Ordering Information
Orde ring Code PI49FCT3807DS Package Type 20- pin 300 mil wide SOIC 20- pin 150 mil wide QSO P 20- pin 209 mil wide SSO P
.025 BSC 0.635
.004 0.101 .010 0.254 .008 0.203 .012 0.305 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
PI49FCT3807DQ PI49FCT3807DH
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
6
PS8493 08/09/00

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